Lifetimes of IC interconnect metallisation under ac stressing (ICIM)
Metallisation failure is a major source of integrated circuit faults, yet the understanding of the physics of their failure are obtained under unrealistic dc stress conditions.
Electromigration failure of integrated circuit metals occurs due to momentum transfer from conduction electrons to metal atoms in the interconnects. This causes gradual atomic movement along grain boundary networks which, over a period of time, can lead to the formation of void and hillocks resulting in rupture and failure.
The failure mechanism is of sufficient importance that CAD design suites include assessments of electromigration vulnerability for each interconnect (e.g. Cadence’s Virtuosity). However, most IC interconnects experience alternating signals, so that the net metal movement ought to be cyclic; delaying or avoiding void/hillock formation. Cyclic stressing of an inhomogeneous line is likely to be more appropriately described then models including the crack propagation model of Coffin and Manson.
The current project seeks to match up low frequency ac stress (1-10 Hz) behaviour, which fits with standard dc understanding, with the current empirical high-frequency (MHz) models, in a manner which includes the known effects of necking, dipping, bumping etc.
This work will deliver a better means of understanding the lifetime behaviour of metallisation and will provide insights into how best to avoid it. It will be useful for CAD tool generators and VLSI Designers.
The project demonstrated that dc models, extended to low frequency ac conditions, describe observed behaviour well. This includes the formation of voids, as current flows in one direction, and heals, as it flows in the reverse direction. It shows clearly that additional processes are at work in ac electromigration failure. Recent results on the effects of processing variations have suggested new modelling approaches to better describe transport/relaxation on the void surface allowing a better parameterisation of this failure mechanism.
Dr Vincent Dwyer - Reader in Electronic Devices
"Reliability measurements of IC metallisation are generally based on accelerated testing which is very different from in-use conditions. While the tests give a good estimate of how mobile atoms are within the interconnect, there are clearly other important mechanisms which dominate the path to metal failure. Using the large database of metallisation test results available in the literature, this project will provide a better understanding of what it is that actually determines failure times."