Project Publication List |
|||||
|---|---|---|---|---|---|
Design for Manufacture Methodology for System in Package Technology |
|||||
| Return to main project list
|
|||||
AUTHOR(S) |
TITLE |
JOURNAL/CONFERENCE |
YEAR |
VOL. |
PAGE |
| N. Strusevich, S. Stoyanov, D. Liu, C. Bailey, A. Richardson, N. Dumas, J.M. Yannou, V. Georgel | Modelling the Behavior of Solder Joints for Wafer Level SiP |
Proceedings of the 8th IEEE Electronics Packaging Technology Conference |
2006 |
127-132 | |
| N. Dumas and A. Richardson | Towards a Health Monitor for System in Package with MEMS Functionality |
Proceedings IEEE International Mixed Signals Test Workshop |
2006 |
151 - 156 | |
| S. Stoyanov, J.-M. Yannou, C. Bailey, N. Strusevich | Reliability Based Design Optimisation for System-in-Package |
8th Int. Conf. on Thermal Mechanical and Multi-physics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSime |
2007 |
289 - 296 | |
| C. Bailey, S. Stoyanov, N. Strusevich, J.-M. Yannou | Reliability Analysis of SiP Structures | Proceedings of HPD'07 | 2007 | 38 | |
| Andrew Richardson, Chris Bailey, Jean Marc Yannou, Norbert Dumas, Dongsheng Liu, Stoyan Stoyanov and Nadia Strusevich | System in Package Technology - Design for Manufacture Challnages | Circuit World | 2007 | 33 | 36 - 46 |
| S. Stoyanov, C. Bailey, N. Strusevich, J.-M. Yannou | Computational approach for reliable and robust system-in-package design | Proceedings of the IEEE 30th International Spring Seminar on Electronics Technology (ISSE) | 2007 | 40 - 45 | |
| C. Bailey, S. Stoyanov, N. Strusevich, J.-M. Yannou | Reliability analysis of SiP structures | Proceedings of 31st International IMAPS Poland Conference & Exhibition | 2007 | ||
| S. Stoyanov, N. Strusevich, J. Rizvi, V. Georgel, J.-M Yannou, C. Bailey | Design for reliability for wafer level system in package | Proceedings of the 2nd IEEE International Electronics System-Integration Technology Conference | 2008 | 1 | 293 - 298 |
| S. Stoyanov, P. Rajaguru and C Bailey | Reduced Order Modelling for Reliability Optimisation of Advanced Micro-Systems | Proceedings of the 2nd International Conference on Engineering Optimization, | 2010 | ||
| J.-M. Yannou, V. Georgel , N. Strusevich, S. Stoyanov, C. Bailey | Combining the SiP and WLP-CSP Trends, State-of-the-Art and Future Trends | Wafer Level Packaging Seminar, 27th June, 2006, Cambridge | 2006 | ||
| J.-M. Yannou et. al. | Silicon Integrated Passives for System-in-Package | EPPIC/NMI SiP Semina, Cambridge | 2007 | ||
IeMRC@lboro.ac.uk - ©2007 IeMRC |
 |
website design by CLANN |
|---|
