Electronic Systems Design Research Group
The group focuses on the design of electronic hardware and embedded software with particular expertise in microprocessor design and machine learning.
The group has three members of academic staff, a research assistant and eight research students. The direction of the group is also formed with the aid of a visiting professor.
The group receives substantial support from the EU, UK research councils and industry. We regularly publish research results in international journals and conferences.
Selex - Galileo
Engagement between Loughborough Uniiversity and CebaTech began in January 2007, when Dr. Chouliaras approached the CebaTech after having read an article on eet.com regarding CebaTech’s unique C-RTL technology called C2R Compiler. After an initial discussion period, CebaTech granted a no-cost license of the C2R Compiler to Dr. Chouliaras and the University in exchange for collaboration on areas of ESL research and the development of complex protocols in hardware.
The following list highlights areas of collaboration over the past three years.
- Proposed recommendations to improve the tool in a number of fronts - Had multiple conversations with Chad and the other experts over the years.
- Contributed in the C2R cookbook the section on advanced parallelism (part of - Chad worked on the other part)
- Designed and implemented two demos for Cebatech, for DAC 08 : One was the FPE2 (floating-point engine), the other was a pipelined SIMD architecture (with an interesting methodology, based on c2r_fork), to accelerate the G723.1 and G729.A speech codecs. They both run on FPGA.
- Published the following
V. A. Chouliaras, Chad Spackman,“LE2: A 2-way LIW/SIMD Coprocessor Designed with an ESL Methodology”,http://www.dspdesignline.com/howto/207400120
Please see the publications list for these people:
Mobile communications for improved monitoring of heart disease and diabetes.
This is a British Council UKIERI project run in collaboration with IIT Delhi, Kingston University, All India Institute of Medical Sciences and Aligarh University. The aim of the project is to exploit mobile communications to improve health care provision for monitoring heart disease and diabetes, which affect millions of people globally.
iFest is an ARTEMIS-JU FP7 European project with the aim of enabling design engineers to explore architectural design space at a high level of abstraction, choose a cost effective design, and from the abstract models produce semi-automatically the hardware and software implementations in a cost effective balance. Loughborough University is working on meta-model extensions to incorporate co-design solutions and collaborating in the development of an instance of the hardware/software co-design flow.
Enosys is an FP7 ENOSYS project to specify and develop a tool supported design flow for designing and implementing embedded systems by seamless integration of high-level system specifications, software code generation, hardware synthesis and design space exploration. Loughborough University’s contribution relates the integration of a extensible processor core into the Axilica flow and the design space exploration of alternative embedded solutions.
Acceleration of FastSLAM for use in small robotic systems.
This work has implemented a fixed-point version of FastSLAM targeting an LE1 configurable extensible VLIW processor. Modifications have also been made to enable fast execution on systems with limited resources
Using visual information to Improve the performance of speech recognition systems in the presence of noise.
The performance of audio-only speech recognition systems deteriorates rapidly in the presence of even moderate audio noise, but can be improved by including visual information from the speaker’s mouth region. The new approach taken here is to incorporate dynamic information captured from the speaker’s mouth occurring during successive frames of video obtained during uttered speech. Audio-only, visual-only and audio-visual recognisers have been studied in the presence of noise and show that the audio-visual recogniser has robust performance.
Hardware implementation of a speech recognition system for use in mobile devices.
This work has identified the most computationally intensive parts of a well-known speech recognition program (Sphinx 3) and implemented these in bespoke parallel hardware. By exploiting such parallelism, the necessary calculations can be completed in a shorter elapsed time and the application can operate at a lower clock frequency, so consuming less power.
An investigation of the architecture and training of asynchronous cellular automata for use in engineering applications.
Visual Speech Recognition
Machine Learning in Hardware