Vassilios is a senior lecturer in microelectronics and embedded CPU architecture in the Electronic Systems Design Group, Systems Division. He conducts research in CPU architecture, Microarchitecture, ESL methodologies and software parallelization.
Keywords
ASIC
VLSI
FPGA
RISC
Embedded CPU
vector processors
vector processors
multithreaded processors
vectorization
Synopsys
Cadence
Xilinx
Axilica
FalconML
Chip Multiprocessors
SS_SPARC
LE1
Leon2
Leon3
SIMD
ARC
Intracom
Design compiler
Physical compiler
Primetime
PRAM
G723.1
G729.A
MPEG2
MPEG4
H264
Trimaran
Simplescalar
FFT
self-timed
micropipelines
Vassilios has been active in the design and implementation of scalar, superscalar and vector embedded microprocessors for over 14 years. Prior to his appointment at Loughborough University in 2002, he was a Senior R&D Engineer/Microprocessor architect for ARC International, working on various hardware projects in the embedded CPU architecture and microarchitectures domains. Prior to ARC, he worked as an ASIC design engineer for Intracom S.A. Prior to Intracom, he developed a 32-bit, 5-stage soft-IP CPU core, compliant with the MIPS-I ISA as the primary product of a private company. He has more than 80 publications in academic journals and international conferences, 5 international patent applications and was the Principal Investigator on an EPSRC-funded project [GR/S44976/01], which researched novel CPU architectures for acceleration of speech coding. He is a founder of Axilica Ltd and the Loughborough PI in the FP7 ENOSYS project.
Vassilios has a number of active research projects in the areas of real-time speech recognition, parametric packet-based interconnects for many-core systems, hardware PThreads, toolchains for ILP processors, embedded system implementations of algorithms for robot navigation and ESL architectures.
View all Dr Chouliaras’s publications in the central publications database
